[mems-talk] Etching Vertical Holes in Si 110 wafer

[Shao Guocheng]

hi, Sudarshan:
  theoretically, because of the hight etch ratio between (110) and (111), you can get vertical wall using (110) silicon. however, the wafer is not perfect, and the crystal direction on the wafer(the flat edge) is slightly different from the actually crystal direction. that may cause you etch process to stop. u should determin the (111) direction accurately before you start to etch for ur structure.  A pair of fan-shape alignment mark may help.  for details, you can check this paper. I used similar method to align for (100) wafer and this process help us to get much better result in term of dimension controll. 
   
  http://ej.iop.org/links/re82lrkph/4OXXwXHs2xG1QDTXav5vpA/jmm6_10_034.pdf
  A crystallographic alignment method in silicon for deep, long microchannel fabrication  T D James et al 2006 J. Micromech. Microeng. 16 2177-2182   doi:10.1088/0960-1317/16/10/034
   
  I hope this helps
   
  Guocheng Shao
  Department of Mechical Engineering
  Louisiana State University

Sudarshan Hegde <hegdesudarshan at gmail.com> wrote:
  The objective is to etch through vertical holes of 100 micron dimension in
Si wafer of 300 micron thickness.
I am using Si 110 wafer.
I have tried out a parallelogram with one of the angles equal to 70.6 and
the other as 109.4.
But each time, I am getting slanted faces which results in stopping of
etching.
Please help me regarding regarding this if at all vertical holes are
possible.