[mems-talk] Integrating a thick dielectric layer surrounding suspended silicon nitride membranes

[Ken Healy]

Thanks to everyone for their suggestions.

Roger -

Yes, I'm proposing to add a thick oxide under the nitride. But, adding a 
thick oxide layer on the back side of the wafer would be equally 
suitable, so long as it covers the etched 111 silicon faces, but not the 
suspended membranes. (I can't see a way to achieve this though, can you?).

The SiO2:SiN selectivity for CHF3/O2 can be up to ~2:1 according to [1], 
but you're right, this is not good enough. I think etching 90% through 
the oxide with CHF3/O2 and then the final 10% with BOE would get close 
to the desired features, but the results with BOE alone should be 
tolerable and simpler to achieve.

Do you have any suggestions for an alternative dielectric material that 
might be easier to incorporate into the membrane fabrication process?


Paul -

I'm aiming to produce 50x50 um or smaller membranes - would you expect 
these to survive the fabrication process?


Michael -

Sorry, I think I misled you by not specifying the requirements for the 
nitride thickness. I need 50-100 nm, which I think rules out the 
possibility of using of thick layer stacks?

As far as I have read, thermal oxidation after nitride deposition is not 
feasible, because above approx. 700 degC silicon atoms begin to 
aggregate. PECVD oxynitride sounds interesting though - can you think of 
a way to keep it off the membrane while depositing a thick layer 
everywhere else?

Regarding the capacitance contribution due to the exposed silicon on the 
sides of the via - yes, the 1-2 nm thick native oxide coating the 
silicon will give a high capacitance, but this will appear in series 
with the much smaller capacitance of the thick dielectric layer, and 
thus make a negligible contribution. Unless I'm missing something?

[1] Williams and Muller, J. Microelectromech. Syst. 5, p. 256, 1996.


Best regards,

Ken Healy

Dept of Physics and Astronomy
University of Pennsylvania