Dear MEMS group,

Our group is building a CMOS sensor array of four sided "buttable" 25mm
"tiles".

1) We will need through-hole conductive vias in our CMOS wafer to bring
power and data through the wafer and connect to a metal layer on the CMOS We
estimate about 20-50 vias per 25mm tile. We are hoping to not lose a pixel
(100um square) at the location of the via, and are thus looking for a hole
less than 50um in diameter, through the 650um wafer.
We want to ensure the via process steps (post CMOS fab)do not damage our
CMOS circuitry.

What processes should we use, and who could do this? Laser drilling? Ion
etch? Electroplate, Conductive paste?


In addition,

2) We need a positioning and mounting technology to mount these (16) tiles
on the precision substrate, with connections up through the vias as
described above. We are hoping of a positioning accuracy of aprox 50um. The
substrate should have a thermal expansion match to the silicon if possible.
(Glass, Silicon, Ceramic?, G-10???)

Does anyone have any experience with this type of mounting? Suggested
vendors?

Many thanks,
Andrew Jeffries
Exxim Computing
925-416-1900