SOI wafers produced by grinding and polishing only go down to about 3 um top
wafer thickness.
Trying to thin such a wafer by further grinding and polishing will be
difficult to control
Thermal oxidation and etching could work, but to consume 2.5 um of silicon
you'd need to grow and oxide about 5 um thick,
which would take a long time (you could also do several oxidations and oxide
etches).

Alternatively, the thickness of the top wafer produced by Soitec using the
Smart Cut process are 0.2 to 1.5 um.
See their Web site.

    --Kirt Williams

----- Original Message -----
From: "Wang Zheyao" 
To: 
Sent: Monday, July 26, 2004 4:52 PM
Subject: [mems-talk] thinning the device layer of SOI wafer


> Hi Guys,
>
> I want a SOI wafer with device (top) silicon layer 0.5 micron, but
> the thinnest device silicon layer of the SOI wafers I can get is 3
microns.
> A method to thin the device silicon layer from 3 microns to 0.5
> micron is to use thermal oxidation or CMP. Does anyone how these
> methods and give me some advice?
>
> Thank you in advance.
>
> Zheyao Wang
>
>
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