Jen,

It sounds like you the PSG may be reflowing during the anneal and exposing
your KOH pit corners.  You may want to try undoped SiO2 or TEOS, or do a
shorter/lower temp anneal.  We have used undoped PECVD SiO2 to passivate KOH
etched pits with fairly good success.


Eric Miller
Laboratory Manager
Washington Technology Center
Ph:  206 616-3855
www.watechcenter.org


-----Original Message-----
From: mems-talk-bounces@memsnet.org [mailto:mems-talk-bounces@memsnet.org]
On Behalf Of Jen Robertson
Sent: Thursday, September 30, 2004 3:08 PM
To: mems-talk@memsnet.org
Subject: [mems-talk] Oxide coating on KOH-etched pits

My device is made by KOH etching large pits on silicon wafers using a
nitride mask. After the pits are etched, 0.5um of silicon dioxide is
deposited by LPCVD to cover the entire wafer.

Etching parameters:
- 6 hours in 80-degree KOH, 30% diluted with water
- etch mask is an LPCVD deposited low-stress nitride

oxide parameters:
- phosphorous doped, deposited at 400C in LPCVD, annealed at 1000C for 30
min.
- thickness 0.5um on horizontal surfaces

We are seeing evidence of electrical leakage through this oxide layer. I'm
wondering if the angled sidewalls etched by the KOH are too rough to be
conformally covered by the oxide. Or maybe the oxide has pinholes, or not
enough coverage at the corners of the pits? Has anyone experience something
similar, or has any recommendations on how to solve the problem?

Thanks!


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