Hi,

I'm going to make some DRIE test on SOI wafer.

To avoid notching effect, there is some special recipes that use low electrode
frequency (380 kHz). So I will try to use the recipe I tested before on S-C-Si
and then switch towards this "SOI mode" just before reaching the SiO2 layer.

The "SOI recipe" used in the lab was optimized for 300nm and uses no switch
(always 90 sccm C4F8 and 40 sccm SF6). I'm now etching 30 microns deep and will
etch 50 microns deep later. So I suppose I will have to optimized that SOI
recipe for my special case.


I don't understand why lowering the electrode frequency avoids SiO2 charging or
at least avoids ions deflection to side wall.

Perhaps some of you know something about that...

Thank you,

Julie.