durusmail: mems-talk: Etching Vertical Holes in Si 110 wafer
Etching Vertical Holes in Si 110 wafer
2007-04-16
2007-04-16
2007-04-16
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2007-04-18
Etching Vertical Holes in Si 110 wafer
Sudarshan Hegde
2007-04-17
Hi Shao
The paper was helpful regarding the methods dealing with perfect aligning.
Thanks a lot.
This paper discusses deep but long channels.
In principle, (given that the alignment is perfect) is it possible to get
vertical holes. i.e., four vertical walls ?
Thanks and regards
Sudarshan Hegde

On 4/17/07, Shao Guocheng  wrote:
>
> hi, Sudarshan:
>   theoretically, because of the hight etch ratio between (110) and (111),
> you can get vertical wall using (110) silicon. however, the wafer is not
> perfect, and the crystal direction on the wafer(the flat edge) is slightly
> different from the actually crystal direction. that may cause you etch
> process to stop. u should determin the (111) direction accurately before you
> start to etch for ur structure.  A pair of fan-shape alignment mark may
> help.  for details, you can check this paper. I used similar method to align
> for (100) wafer and this process help us to get much better result in term
> of dimension controll.
>
>   http://ej.iop.org/links/re82lrkph/4OXXwXHs2xG1QDTXav5vpA/jmm6_10_034.pdf
>   A crystallographic alignment method in silicon for deep, long
> microchannel fabrication  T D James et al 2006 J. Micromech. Microeng. 16
> 2177-2182   doi:10.1088/0960-1317/16/10/034
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