Hi TK
Have you tried etching the box layer after you create the hole in the membrane?
Best
Leo

On Thu, Oct 23, 2008 at 12:00 PM, Taekyung Kim  wrote:
> Hello Folks,
>
> I have a problem with SiO2/Si etching.
>
> After Bosch etching from the back side of 400 um thick SOI wafer, 120 um x
> 120 um square membranes (SiO2 100 nm/Si device layer 3 um thick) were made.
> Buried oxide layer was HF-vapor etched.
> On the front side, I have a 10 um long, 250 nm wide Pt/Cr metal line and
> want to suspend this metal beam by etching SiO2/Si.
> Only 10 um long 5 um wide rectangle around the metal beam must be etched,
> not the whole membrane area.
>
> After electron beam lithography to define a etching window, the sample was
> immersed in 1:6 BOE for 90 s (90 nm/min etch rate) and 25% TMAH at 70C for
> 12-13 min.
> The problem is after TMAH etching, the whole 120 um square membrane was
> damaged or etched maybe because once a window opens up on the bottom of Si
> device layer, TMAH etches Si from the back side as well.
>
> Any idea to control Si etching?
> I desperately need to have SiO2/Si membrane with 10 um/5um rectangle
> thru-etched window.
>
> Thanks
>
> TK

--
Xiaoguang "Leo" Liu
Birck Nanotechnology Center,
Purdue University,
1205 W.State Street, West Lafayette, IN, 47906 USA
liu79@purdue.edu