The problem you are describing is known as RIE Lag. It isn't unique to
XeF2 etch nor is it due to the gas inlet holes.

There is an excellent paper which covers this issue and an overview of
more advanced plasma etching at IBM.

http://www.research.ibm.com/journal/rd/431/armacost.html

Search for the term RIE lag. Or aspect ratio. It is a long paper.

You don't mention whether you are using a diode/triode plasma or an
inductively coupled plasma (High density plasma etching).

Edward H. Sebesta
Independent Semiconductor/MEMS Engineer



-----Original Message-----
From: mems-talk-bounces@memsnet.org
[mailto:mems-talk-bounces@memsnet.org] On Behalf Of junjun wu
Sent: Saturday, February 21, 2009 2:47 PM
To: General MEMS discussion
Subject: [mems-talk] XeF2 etching of Si


Hi,

I'm using XeF2 to etch a Si wafer that has different feature sizes
(squares) on the same surface, like 1mm, 0.3mm, 0.1mm etc. I found that
the etch rate decreases as the feature size decreases. I used 3 torr of
XeF2 for 30 sec and various cycle numbers. I wonder if this is common
with XeF2 etching or has something to do with the patter of the gas
inlet holes over the wafer surface. Please advise if there are any ways
to obtain uniform etch rate on different feature sizes on the same wafer
surface using XeF2.

Thanks,

--
Junjun Wu
Twin Creeks Technologies