Hello mems-talk community,

I have some "after release" or "during release" issues in my process.
I am using a sequence of wet etchants to release my free standing structures..
The last etchant is Buffered Oxide Etch (BOE) (6:1) for ~120 minutes.

During that BOE (6:1) etch, I am etching 2 micron thick thermal oxide
from the BOX layer of my SOI wafer. I did not think about that before
I had that issue, but from my point of view, it really matters from
which layer the BOX layer is grown, and how thick it is grown...

Depending on how thick the BOX layer is, and depending on from which
layer you choose to grow it (we have two options for that: 1. from
device layer, and 2. from handle layer) the bowing/warping effect
(magnitude and direction of tensile/compressive stress) can be
controlled or at least can be tailored close to what you want to have.

In addition to those controllable parameters, if we choose to grow the
BOX layer from the "handle layer", we can choose to leave the back
side of the handle layer with the grown oxide rather than removing
this oxide away from the back side of the handle layer. But, in my
case, I do not want to deal with that problem, and I want to choose an
SOI wafer with oxide "only" in the BOX layer, but not on the back side
of the handle layer.

So, my SOI wafer will look like something below:

Device layer (10, or 20 micron thick Silicon)
BOX layer (grown from Device or Handle layer, grown for ???? nm thickness)
Handle layer (500 microns thick Silicon)

Before going further, I want to give you some definitions which I hope
will simplify our communication:

The symbol '._.' will stand for an SOI wafer "bowed up" (edges are at
a higher level compared to the central region of the wafer) when you
keep your SOI wafer handle layer touching your hand's palm, and
looking the device layer of the wafer from the top.

Similarly,

The symbol _.-._ will stand for an SOI wafer "bowed down" (edges are
at a lower level compared to the central region of the wafer) when you
keep your SOI wafer handle layer touching your hand's palm, and
looking the device layer of the wafer from the top.

and,

The symbol --- will stand for a neutral (flat), or almost neutral
state SOI wafer.

Since thermal oxidation is a volume increasing process, when you grow
the oxide from the "device layer", I think the final shape of the SOI
wafer becomes as '._.' "bowed up", and we fabricate all our steps on
such an SOI wafer. However, when you come to the release step, you
etch the BOX layer, and the SOI wafer wants to neutralize the stress,
and wants to come to --- state. This causes micrometer/nanometer order
relative movements between the device layer and handle layer. While
this release process neutralizes the stress on the wafer itself, it
causes "tensile" stress on your free standing "released" structures
because they are microfabricated in '._.' "bowed up" state SOI wafers,
and then transferred to --- state. In my case, this stress was so
strong, it fractured my free standing thin-film layers.

I believe, but I am not sure, and I want to ask your opinion with your
supporting reasons:

If I choose to use an SOI wafer with BOX layer grown from the "handle
layer", then the stress state should be _.-._ "bowed down" because of
the increased volume during the oxidation process. And after the
release, I should have compressive stresses on my free standing thin
layers which will not fracture my samples, but will try to buckle my
thin and free standing films. I can deal with compressive stresses
that want to buckle my films, but the opposite is not possible because
I already loose my samples since they are fractured...

Thanks in advance for your help, and I am looking forward for your replies,

Mehmet
Mechanical Engineer