Hello Zhijian,

First of all, I am sorry, I could not see your e-mail although I checked
my e-mails regularly.

Yes, I was concerned about the stress issues at the silicon/oxide interface.
But, later I started thinking that this might not be the only reason for
the stress issues.

I am getting my SOI wafers already annealed before I do any processing
on them.

After getting my SOI wafers, then, I am depositing a stack of  Cr (10nm)
/ Au (100nm) / Cr (25nm) / Carbon (150nm) / Oxide (5nm) layers.
Cr, Au, and Oxide are e-beam evaporated, while Carbon is PECVD deposited.
First layer on the Si substrate is 10nm Cr as adhesion layer, and last
layer is 5nm Oxide.

I started suspecting that the main reason for the stress issues is that
stack of layers. (In case you wonder, I did not do any stress
measurements after depositing all those layers)

Do you have any suggestions about that multi-layer structure?
In case you wonder how my release  process steps are, I am writing them
below:

Before I do the release, I have only Cr (10nm) / Au (100nm) / Cr (25nm)
as thin layers. So, I am removing Carbon (150nm) / Oxide (5nm) before
the release process is performed.

Then, I am using CR14 to etch Chromium. So, I have only Cr (10nm) / Au
(100nm) on my substrate.

Then, I am using Isotropic Silicon Etchant (HNO3 : H2O : BOE(30:1) = 126
: 60 : 5)  for a very short time (1 minute) just to get rid of the sharp
edges caused during BOSCH process.

After that, I am using BOE(6:1) for ~100 minutes to etch the BOX layer
oxide and release my structures.

Then, I am using a Critical Point Dryer tool to make sure that I do not
have any stiction issues.

The only time I check whether my structures are released is after the
Critical Point Dryer process is finished. So, I am checking my
structures only in the end of all the release steps.

Next time, I will check my structures after every wet etch step, but I
do not expect to see any problems because the structures are still fixed
to BOX layer.

I think, whatever happens, happens in the BOE etch step.

What do you think? Do you have further suggestions?
I am looking forward to your reply.

Best regards,

Mehmet

Zhijian ZHOU writes:

Dear Mehmet,

I think you are talking about the stress issue generated at the
silicon/oxide interface. As far as I known, firstly, this interface
should not have a big stress problem. And if you are sure that the
stress indeed happens at this interface, then a high temperature
annealing would help. Idealy, higher than 900 degree C, during the
annealing, the oxide layer will reflow, which you can imagine a water
flow between your bulk substrate and si device layer. So, any stress at
this interface should be released. If your device can bear, say, 1000
degree C, possibly there will no stress problem.

Hope this can help you.

Sincerely,
Zhijian ZHOU
HKUST