Weiquan

I and my friend, Jie Liu (he specifically works on SOI) worked on back side
etching. I don't know how thick you want to etch. We use anisotropic Si etch
(Bosch process), and it gives good result and vertical etching. The tool is
Plasma therm ICP etcher. I found out this to be very useful. The selectivity for
Si and SiO2 was 100:1. The only problem with dry etch may be its slow etch rate.
Eching rate for me was 0.25-0.3um/min. For etching 500 um Si I found that only
6um SiO2 was etched. The SiO2 was Plasma Therm PECVD oxide. The staffs in
cleanroom told me that the oxide from that specific tool is the worst from all
PECVD deposition tools they have. As the top side was placed upside down, I
didn't find any etching effect on the top side SiO2.. The work is done in
MiRC,GTech, Atlanta. Any further questions are welcomed.


Muhammad Qazi
Dept of EE
University of South Carolina, Columbia



-----Original Message-----
From: weiquan yang [mailto:quanwy@gmail.com]
Sent: Wednesday, May 05, 2010 11:26 AM
To: General MEMS discussion
Subject: [mems-talk] Etching SOI wafer from back side

I want to etch away the Si base substrate of SOI wafer from back side and
remain the top thin Si layer and buried oxide layer.  I try the wet etching
in both ways (using TMAH or KOH solution). The SiO2 or Si3N4 deposited by
PECVD were used as protection mask layers (both side: top and back). However
SiO2 or Si3N4 can not survive very well in the hot sulution for long term
(several hours). Some local areas of top Si layer of SOI was etched
away. Could you guys kindly give me some suggestions? Is this due to the
quality of SiO2 or Si3N4 layer? The quality of SiO2 or Si3N4 by PECVD may be
not very good , so the SiO2 or Si3N4 can not survive.
Some dry etching suggestion is aslo welcome.

Thank you!

Weiquan Yang
EE department
University of Texas at Arlington