Thanks, Robert,
I will try that.

Cheers,
Marcel

Robert Ditizio schrieb:
> Marcel:
>
> It is not surprising that you "did not get significant results" with
> your RIE system.  You do not describe the configuration of your RIE
> system but if it is not inductively coupled, and does not have the large
> power supplies typical of ICP-based DRIE systems, then it is likely that
> you are getting very low etch and passivation rates.  In order to get a
> deep silicon etch process out of this system, you may need to approach
> the development a little differently.
>
> You might consider collecting an etch rate for the silicon with SF6 to
> determine the duration required for the etch step of the cyclic Bosch
> process.  Running a process for 7sec is not as relevant as running for a
> duration sufficient to etch a target etch depth into the silicon.  A
> typical depth for the etch step, for example, might be 0.5 to 1um.  You
> will want to target the duration of the SF6 etch step to reach this
> depth.  If your silicon etch rate is only about 1um/min, then your SF6
> etch step would need to be run for 60sec, not 7sec, in your reactor.
> The ultimate duration will depend on the sidewall roughness that you can
> tolerate for your application but these numbers are provided as an
> example.
>
> For the passivation step, you will need to set the duration of the CHF3
> passivation step so that you get sufficient sidewall coverage to prevent
> isotropic etching of the sidewall.  You may need to try a few different
> deposition times to determine the time required to provide sufficient
> coverage to prevent sidewall attack, without overdoing the exposure.
> Too much deposition will lead to narrowing of the opening.  It is also
> important to remember that you need to remove the passivation from the
> bottom of the trench at the start of each SF6 step before you can
> continue with the etching of the silicon.
>
> You don't mention if you are biasing the wafer but you will need to have
> the substrate biased to get a reasonable etch rate for the silicon.  You
> also don't mention anything about the pressure range that you can
> operate.  Typical pressures for deep silicon etching fall into a very
> wide range, from 30 to >200mT.  If your etcher is capacitively coupled,
> you are likely to be limited to upper end of this range.  Most deep
> silicon etch processes run at high gas flow rates of hundreds of sccm.
>
> The process in the original Bosch patent was described using SF6 as the
> etchant and CHF3 as the passivant, so there is precedent in using this
> combination. Good luck with your process development.
>
> Robert Ditizio
> Tegal Corporation