Hello Rob,

In response to your question regarding acceptable alignment tolerance
for wafer bonding. This depends on the tooling that you are using and
the type of bond that you are performing. The type of tooling that you
describe, requiring the withdrawal of flags after alignment, can be
problematic for many types of bond, especially those in which there is a
softening of the interface bond layer (ie adhesive bonding, glass frit
bonding and some eutectic bonding). For these bonds and flag-based
tooling then 20um alignment is a reasonable target. However for the case
of in-situ aligner bonders, there are no flags to remove and better
alignment tolerances can be achieved. Provided that the wafer bow is
within SEMI specifications, the alignment accuracy for the above bond
types using in-situ alignment can be <3um. For direct bonding and
thermocompression bonding then in-situ alignment can produce reliable,
post-bond 1um alignment accuracy.


Anodic bonding is a different case given that there is a fundamental and
finite TCE difference between the borofloat glass and the silicon which
can result in a run-out of ~80ppm per degree. This can cause a
mis-alignment of ~5um.

Regards

Tony Rogers
AML

-----Original Message-----
From: mems-talk-bounces+tony=aml.co.uk@memsnet.org
[mailto:mems-talk-bounces+tony=aml.co.uk@memsnet.org] On Behalf Of
Robert MacDonald
Sent: 02 September 2010 21:27
To: mems-talk@memsnet.org
Subject: [mems-talk] Wafer bond alignment tolerance[Scanned]

This is regarding bond alignment. I am basically interested in taking
a poll regarding what people think reasonable bond alignment tolerance
is. I know my own experience, and have spoken with a few engineers who
have done bond process development. For myself, I found that I had to
design my process to tolerate up to 20um of misalignment, and even so, I

have about 1 out of 10 wafers falling out of spec. I'm wondering what
others have encountered. One engineer I spoke with told me that they
specified 25um, but they also had poor quality. I run a bond process on
a standard commercially available bonder. The process is an anodic bond
between Si and borofloat wafers both of which are patterned. I use flags

(shims) to separate the wafers during ramp, and pull them out prior to
bonding. The wafers are 100mm. I measure the misalignment using a
shear-image tool, accurate to within .25um. My process can tolerate up
to 20um of absolute misalignment at either of the alignment marks
located on a diameter of 90mm. I am looking for others who have done
serious process development in wafer bonding with alignment who would be

willing to share what tolerance they were able to hold the process to.
The reason I ask, and applications engineer has told me that 1um
misalignment was possible.

Rob MacDonald
Shearwater Scientific