durusmail: mems-talk: DRIE problem in etching high resistivity silicon substrate
DRIE problem in etching high resistivity silicon substrate
2010-09-14
2010-09-15
DRIE problem in etching high resistivity silicon substrate
dyqiao@nwpu.edu.cn
2010-09-14
Hi everyone ,

        We are now etching holes through silicon wafers. When we are using low
resistivity silicon wafers, the sidewall profile can be perfectly controlled,
but when using high resistivity silicon wafers, very serious undercut was
observed at a depth only about 50 micron when Al was used as etching mask. So,
is this phenomenon caused by the charge accumulation due to the high
resisitivity or anything else? Anybody has experienced this and has a solution?
Thanks.

----------------
Sincerely yours,
Dayong Qiao, Ph.D.
M/NEMS Lab.
Northwestern Polytechnical University
Xi'an, China 710072
http://mems.nwpu.edu.cn

Tel: 86-29-88460574(Fax)
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