Dear all,

   I have deposited a SiO2 passive layer on n-GaN without annealing (RTA
facility did not work). But that the passive layer is fragile for
postprocessing. I want to fabricate mental line on this layer, but when
lifting off the photoresist in developer, some cracks showed up. It seems
that the deposited thickness is the key issue which affects the quality of
SiO2.

   Anybody familiar with this field please give some suggestions.

--
Sincerely
Jack, Zetao MA
Dept.of EEE, CYC712,HKU