I am currently using the AMI 1.2 process technology.  Open is not
defined for this process and so you have to construct it by stacking
the glass, via, substracte contact, and active area yourself.  I have used
the Orbit 2.0 in the past. It is not easy to get process information
(which is related to dimensional information) since it is proprietary.
You can use the electrical characterizations from the run to get
dielectric thicknesses.  The best way is to make your own cross sections.
Please contact me directly if you would like to discuss further.

Michael Gaitan

NIST Non-Conflict of Interest Statement: NIST does not recommend one
commercial product over another.

On Wed, 17 Mar 1999, John Patrick Bedell wrote:

> Hello everybody,
>       I am interested in using XeF2 to etch silicon on a CMOS chip, and
> would like to know which MOSIS processes support an open layer of exposed
> Si substrate for this etching.  More generally, I'd really like to get
> detailed cross-sections and layer thicknesses for CMOS processes available
> through MOSIS. Does anyone know where this information might be available?
>       Thanks!
>
>       Patrick Bedell
>       jpb@mrsc.ucsf.edu
>       (415) 476 1910
>
>
>
>