In microelectronics, pad ox. generally refers to a thin thermal oxide layer
used as a stress compliance layer underneath LPCVD silicon nitride, when the
nitride is deposited onto silicon. An example is nitride used as a hardmask
for Si trench etch. Apparently, the silicon surface is in better shape after
stripping the hardmask, if a oxide has been used as a buffer. Since trench
etch is pre-gate oxide, the silicon surface quality is critical. It is
generally stripped with BOE (Buffered Oxide Etch).

Best regards,

David Kinosky
Reveo, Inc.
3 Westchester Plaza
Elmsford, NY 10523


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Today's Topics:

   1. Pad etch (Karen Smith)

--__--__--

Message: 1
From: "Karen Smith" 
To: mems-talk@memsnet.org
Date: Wed, 10 Oct 2001 17:18:53 +0000
Subject: [mems-talk] Pad etch

I have seen several references to "Pad etch" in
micromachining literature - specifically relating to
removal of a sacrificial oxide layer.

I have asked several chamical suppliers and checked
in several references to  no avail (I believe it
is a specialisat formulation (HF?) by Ashland, but
can find no reference to it on their MSDS?).

Can anyone help me with what it actually is & who
supplies it?

Best regards,

Karen Smith
MST consultant
Coventry, UK

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