durusmail: mems-talk: wafer level vacuum packaging
wafer level vacuum packaging
2002-03-18
2002-03-18
Hexsil process
2002-03-18
cantilevers
2002-03-19
2002-03-20
2002-03-20
2002-03-19
Stero lithography service.
2002-03-21
wafer level vacuum packaging
RobDavis
2002-03-18
We are in the prototype stages of a total silicon carbide package and chip
for extreme service.  Silicon carbide is good as a semiconductor over 600C
and our resistors good to 1000 C using high temperature contacts.  The
package is made from polycrystalline silicon carbide wafers and sealing is
done in a controlled atmosphere furnace.

Rob

-----Original Message-----
From: mems-talk-admin@memsnet.org [mailto:mems-talk-admin@memsnet.org]On
Behalf Of Mike Mattes
Sent: Monday, March 18, 2002 7:30 AM
To: mems-talk@memsnet.org
Subject: Re: [mems-talk] wafer level vacuum packaging


Has any company actually commercialized a product using wafer level
packaging?

Best Regards,
Mike Mattes
Medtronic, Inc.



>>> krishna@san.rr.com 03/15/02 04:56PM >>>
I am interested to know if anyone can send me information regarding
techniques, companies, research etc. in this area.

Krishna Kashyap
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