Consider electroless plating.  For Cu, dip in a Pd-Sn colloid and then into
the plating solutions.  You can formulate your own or buy it off the shelf
from companies like Enthone-omi or Technic.

-----Original Message-----
From: Frank Rasmussen [mailto:FRA@mic.dtu.dk]
Sent: Friday, August 16, 2002 5:51 AM
To: mems-talk@memsnet.org
Subject: SV: [mems-talk] CVD deposition of metal needed !


Thank you for your input Neal, Kirt and Bob.

Just to clarify a bit:
The requirement of low temperature is set by the Parylene C insulation
material, which is able to withstand around 300 degrees centigrade. The
reason I can't use thermal oxide or similar processes for the insulation of
the wafer through-holes is that the wafer through-holes have to be
fabricated as a post process on CMOS wafers (I have considered PECVD TEOS
oxide as well, but I'm not sure if the quality of this material is
sufficient).

The wafer through-holes are almost vertical and therefore difficult to coat
using PVD. Though, it might be worth considering a modification of the ICP
etch process in order to provide a tapered profile.

Thanks again,
Frank
------------------------
Frank Engel Rasmussen
Industrial Ph.D. student, MEMS research group
Mikroelektronik Centret
Oersteds Plads
Building 345 (east), DTU
DK-2800 Kgs. Lyngby
Denmark