durusmail: mems-talk: CF4 / O2 Silicon dry etch
CF4 / O2 Silicon dry etch
2005-06-21
2005-06-21
CF4 / O2 Silicon dry etch
Hongjun-ECE
2005-06-21
Try the following and see if they help,

1. Add some He
2. Increase the chamber pressure
3. Make the wafer thermally contact very well to the base, i.e, using some
thermal conductive glue.
4. Just for curiosity, for Si etch, why not try SF6?

Good luck,

Hongjun Zeng, PhD
Microfabrication Application Laboratory(MAL)
University of Illinois at Chicago
3014 ERF Building, 842 W. Taylor Street
Chicago, IL 60607
Tel. 312-413-5889, Fax: 312-413-0447


-----Original Message-----
From: Jason Milne
Subject: [mems-talk] CF4 / O2 Silicon dry etch

I'm doing some research into fabrication of silicon microlenses (~400
microns diameter, ~15 microns high) by photoresist reflow followed by
transferring the resist profile into the silicon substrate with a dry etch
using CF4 / O2 plasma.

Everything is working fine, except that the surface of my lenses looks like
the surface of the moon. They are covered with circular pits of different
sizes, up to about 4 microns diameter and 100 nm deep.

I have been unable to track down the source of this problem in the
literature. If anyone knows of the origin of this surface damage, advice
would be greatly appreciated.

Attempting to isolate the origin of this damage, I have drawn the following
conclusions that may help diagnose the problem:

- Photoresist surface is fine before dry etch

- Pits are occurring in the photoresist during the dry etch and are
subsequently transferred into the silicon substrate

- Damage is independent of RF power over the range 50W-200W and ICP power
300W-750W

- Damage still occurs when temperature of resist surface does not exceed
85 degrees Celsius during dry etch

- Damage still occurs if resist lenses are left for 24 hours before dry etch

- If the resist lenses undergo a further high-temperature bake after reflow
(5 mins bake, temperatures of 165, 185, 205 and 225 degrees), then the
damage gets worse as the temperature of this bake is increased.

My process parameters:

AZ4562 resist

Reflow at 145 degrees Celsius for 10 minutes

CF4 conc. 20sccm

O2 conc. 3sccm

RIE powers: 50W, 100W, 200W

ICP powers: 300W, 500W, 750W

Pressure 10mTorr

I also have photos of the silicon surface, if these would help shed light on
the situation then please email me.
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