Ken,

As I understand, the modification you're making is the addition of the
thick oxide under the nitride.  Growing such a thick oxide will take a
long time e.g. ~49 hours for a wet oxidation at 1100 degC.  An
alternative might be to use an oxide or other dielectric deposited by
CVD.

If you use SiO2 as a dielectric it might be better to wet etch with BOE,
since the CHF3/O2 RIE will probably etch the nitride faster than the
nitride.

Roger Shile

-----Original Message-----
From: mems-talk-bounces@memsnet.org
[mailto:mems-talk-bounces@memsnet.org] On Behalf Of Ken Healy
Sent: Monday, June 02, 2008 11:41 AM
To: mems-talk@memsnet.org
Subject: [mems-talk] Integrating a thick dielectric layer
surroundingsuspended silicon nitride membranes

Hello,

I'd like to ask for advice on how best to modify the standard procedure
for fabricating suspended silicon nitride membranes to incorporate a
thick dielectric layer (>=5um).

The aim is to reduce the capacitance from the top to the bottom of the
chip supporting the membrane, as it will be used to separate two
chambers of conductive fluid. The capacitance with standard membranes is

very high since the thickest dielectric layer is the thin silicon
nitride (50-100 nm in my case).

Reducing the fluid contact area will reduce the capacitance, but the
microfluidics required to achieve an equivalent reduction in capacitance

appears more complicated than adding a dielectric layer.

(The particular application I'm working on is nanopore-based DNA
analysis, where the noise level scales with capacitance. For background
info see http://eleceng.ucc.ie/nanopore/)


The best process I have come up with so far is as follows, but it's
still significantly more complicated than the standard procedure for
silicon nitride membrane fabrication. See the diagram below for
reference.


membrane nitride
======================================================================
dielectric oxide               |        |
--------------------------------        ------------------------------
                               /          \
                              /            \
silicon                     /              \
                            /                \
                           /                  \
--------------------------                    ------------------------
mask oxide               |                    |
==========================                    ========================
mask nitride


1. Grow 5 um thermal oxide on 100 silicon wafers (on both sides to avoid
wafer bow due to stress)

2. Grow 50-100 nm low-stress silicon nitride on top of the oxide

3. Follow the standard membrane fabrication procedure to define openings
in the mask nitride layer.

4. Anisotropically etch the mask oxide layer with CHF3/O2 plasma,
protecting the silicon nitride with photoresist.

5.KOH-etch the silicon following the standard membrane fabrication
procedure.

6. Finally, etch the exposed dielectric oxide with CHF3/O2, protecting
the membrane silicon nitride with photoresist.

7. Remove any fluoropolymer residue resulting from the CHF3/O2 etch
with oxygen plasma.

Any suggestions would be greatly appreciated.