durusmail: mems-talk: Thinnest Cr layer that can still successfully adhere Au to Si
Thinnest Cr layer that can still successfully adhere Au to Si
Thinnest Cr layer that can still successfully adhere Au to Si
Mehmet Yilmaz
2009-08-28
Thanks for the e-mail Felix.

I do not have full control on deposition rate. Sometimes it is
fluctuating very fast, but I try to keep it ~0.5 Angstrom/sec. In the
worst case scenarios my deposition rate varies between 1 Angstrom/sec
and 0.3 Angstrom/sec.

Unfortunately I do not have control on substrate temperature, I can only
observe how high or low is the temperature on my substrate... But, I
have never observed it up to that point.

Could you please explain what you mean by plasma treating the surface?

The thickness of gold in this case was 100nm. So, I guess this should
not be a problem. But, now I am planning to work with 40nm thick gold
instead of increasing the thickness. I hope this should not be a problem
too. What do you think?

Formula of the Cr etchant is CH3COOH + Ce(NH4)2(N03)6 + H20.
8% acetic acit, and 22% ceric ammonium nitrate (the rest must be water I
guess). Its name is CR-14.

I made a test to understand if Cr is etched in 49% HF. There was no
damage on Cr surface after 2-3 minutes in 49% HF. I did not keep my
test wafer more than 2-3 minutes in 49% HF...

I also could not understand what you suggest in galvanic etching. Do you
mean, I should try galvanic etching, or do you mean that the reason for
my problem is galvanic etching?

Just before the final Cr etching, my wafer is exposed to polysilicon
etchant (126 units HNO3, 5 units BOE(30:1), and 60 units DI Water).

But, if you ask me the Cr and Au deposited region before I deposit Cr/Au
layers: the surface is exposed to CHF3/O2 plasma to etch a nitride layer
from the region that I am depositing Cr/Au layers...

In addition, the same Cr/Au layer region is exposed to Oxygen Plasma as
a descum process to make sure that I will remove residual PR particles
from my wafer surface before I deposit Cr/Au layers that I am going to
pattern with a lift-off process.

I hope my explanations are clear...

Thanks in advance again,

Mehmet



Felix Lu wrote:
> Dear Mehmet,
>
>    We have had success using thinner Cr adhesion layers (we used 5 nm
> and 3 nm) for gold adhesion, so I'm guessing that the percolation
> thickness for chrome is thinner than that (anybody know?). That being
> said, I know some foundries use much thicker Cr layers for their gold
> processes. I believe you can push the percolation thickness of chrome to
> thinner values by increasing the Cr deposition rate (incidentally, what
> is your Cr dep rate?), lowering the substrate temperature if your
> evaporator has this feature, or by plasma treating the surface.
> If you're having problems with pinholes in the gold allowing the etchant
> to attach the Cr, going to thicker layers of gold seems to help. How
> thick is your gold?
>
> I'm not familiar with the chemistry of the chrome etchant but another
> possibility is galvanic etching. We've seen this in 49% HF, with it
> being more prominent at lower base pressures (~2e-6 Torr vs 4.9e-6 Torr)
> suggesting that some chrome oxide might be good for adhesion!
>
> Also, what other chemicals is your wafer exposed to before the final
> chrome etch?
>
> Felix
>
reply