durusmail: mems-talk: Wafer bond alignment tolerance
Wafer bond alignment tolerance
2010-09-07
Wafer bond alignment tolerance
Robert MacDonald
2010-09-02
This is regarding bond alignment. I am basically interested in taking
a poll regarding what people think reasonable bond alignment tolerance
is. I know my own experience, and have spoken with a few engineers who
have done bond process development. For myself, I found that I had to
design my process to tolerate up to 20um of misalignment, and even so, I
have about 1 out of 10 wafers falling out of spec. I'm wondering what
others have encountered. One engineer I spoke with told me that they
specified 25um, but they also had poor quality. I run a bond process on
a standard commercially available bonder. The process is an anodic bond
between Si and borofloat wafers both of which are patterned. I use flags
(shims) to separate the wafers during ramp, and pull them out prior to
bonding. The wafers are 100mm. I measure the misalignment using a
shear-image tool, accurate to within .25um. My process can tolerate up
to 20um of absolute misalignment at either of the alignment marks
located on a diameter of 90mm. I am looking for others who have done
serious process development in wafer bonding with alignment who would be
willing to share what tolerance they were able to hold the process to.
The reason I ask, and applications engineer has told me that 1um
misalignment was possible.

Rob MacDonald
Shearwater Scientific

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