All,

Last year we run a project in which we used ls SiN as BOX layer for SOI
instead of oxide.


Regards,

Peter Kuijpers
Process Engineer
Philips Innovation Services
MiPlaza/TL group
High Tech Campus 04-p5.12
5656 AE Eindhoven
The Netherlands
Phone: +31 402743667
Mobile:+31 612507027, Mobex: +31 402798904
Email: p.e.m.kuijpers@philips.com



-----Original Message-----
From: mems-talk-bounces+p.e.m.kuijpers=philips.com@memsnet.org [mailto:mems-
talk-bounces+p.e.m.kuijpers=philips.com@memsnet.org] On Behalf Of
my2232@columbia.edu
Sent: Tuesday 18 January 2011 6:10
To: mems-talk@memsnet.org
Subject: [mems-talk] stress state of photoresists

Hello mems-talk community,

I have a question about the stress state of resists after they are
developed, and ready for masking purposes.

To give an example related to my question:

I am working with SOI wafers, and the BOX oxide is in compressive
state of stress. Hence, once you remove some parts of the silicon
layers from certain places of your wafer (espacially if the silicon is
removed from same location of both sides of the BOX layer) you will
see that the BOX layer oxide will tend to have wrinkles, which
indicates that the BOX oxide is in compressive state, and once it is
free to move it will buckle up and down to change its stress state.

Now, my questions is:

What would be the case if we were using resist as BOX instead of
thermal oxide as BOX? Would it be in compressive stress, and buckle up
and down, or would it be in tensile state of stress and keep staying
in completely flat (no wrinkles at all) state?

The result may depend on the resist we are using, but I would be glad
if someone can tell me if there is a resist with tensile state of
stress?

I am looking forward to your replies, and
Thanks in advance,

Mehmet Yilmaz
Mechanical Engineer