Hi Rob

That is because the rough surface of Au and Al, so there is UV reflection to
the via hole. Then the via hole is exposed.

Thanks
Ning

2011/2/2 Robert James 

> I am having a problem patterning SU8 on alumina substrates on top of a
> patterned gold film.
>
> I have some polished alumina substrates (approx 250 microns thick) with a
> thin film (~1 micron) gold pattern on the top surface.  I am trying to
> pattern SU8-3005 (approx 4 microns thick) as an interlayer dielectric on
> top
> of the gold.  The SU8 pattern includes openings that are all on top of gold
> features.  Using our current process, where the edge of the opening is
> adjacent to a larger field of metal, the pattern develops out nicely in
> about 5-7 minutes.  Where the edge of the opening is adjacent to the edge
> of
> the metal, the pattern doesn't develop properly, even with extra long
> development times (>30 min).  This is most evident where (for example) a 50
> micron square via is patterned in SU8 at the edge of a 200 micron wide Au
> line such that 3 sides of the via have a large field of metal adjacent to
> the edge of the via, while the 4th edge is on top of the gold but adjacent
> to bare alumina.  Three sides develop out properly, but a significant
> amount
> of SU8 is left in the pattern along the fourth side of the via.  This
> effect
> is independent of pattern orientation.  Note that large features (>100
> microns) develop properly using our current process; smaller vias (even as
> large as 35 microns), don't develop out at all.
>
> Has anybody else seen this effect?  Is the problem likely to be related to
> exposure control, thermal management or something else?  Any help or clues
> as to how to address it would be greatly appreciated.
>
> Thanks,
> Rob