Dr. Zhou,

Best results are going to be by using RIE
(reactive ion etching) and preferably
DRIE (deep reactive ion etching)..... instead
of KOH etches. However, KOH can be used for
at least your 10 micron deep basins.

Steps:

(1)  Coat wafer with RIE photoresist on front side
(2)  Expose to Mask #1 (this mask only has
     the 10 micron deep basins patterned into it)
(3)  Develop
(4)  RIE or KOH etch the 10 micron basins
(5)  Remove photoresist
(6)  Coat wafer front side with more RIE photoresist
     (this resist is quite thick, and should conformally
     cover the 10 micron step at the edges of the basins
     with no problem)
(7)  Expose to Mask #2 (this mask has the 50 micron
     deep trenches patterned into in... with alignment
     marks for registration). Align using infra red
     to see through the photoresist
(8)  Develop
(9)  DRIE the 50 micron deep trenches
(10) Remove photoresist
(11) Coat back side of wafer with RIE photoresist
(12) Expose to Mask #3 (this mask has only the
     narrow through-holes patterned into it..... with
     infra red alignment marks)
(13) Develop
(14) DRIE the through-holes from the back side
(15) Remove photoresist
(16) You're done!

Good luck,

brian hubert, micromedia, mit media laboratory


> ---------- Forwarded message ----------
> Date: Fri, 13 Aug 1999 23:42:50 -0500
> From: Xiaochuan Zhou 
> To: MEMS@ISI.EDU
> Subject: Help on processes
>
> Dear colleagues:
>
> I would like to get suggestions on fabrication processes.  I am designing a
> process for fabricating a device containing three levels of etched features
> on a silicon wafer.  The features include basins of about 10 micron deep,
> trenches of about 50 micron wide and 50 micron deep, and narrow
> through-holes (etched all-the-way through the silicon wafers of 300 to 450
> micron thick).  I am considering the use of Si(110) substrates and KOH wet
> etching for achieving the arrow through-holes.  It seems that I have to go
> through at least three etching steps in order to achieve three levels of
> depth.  My difficulty is at the photoresist coating between the steps.  Any
> one of my device features would cause sufficient corrugations on the
> substrate surface and make uniform photoresist coating impossible.  I would
> like to hear any suggestions on the overall process design, suitable etching
> processes (wet or dry), and any tricks and/or materials that may make the
> fabrication easier.
>
> Thank you very much.
>
>
>
> Xiaochuan Zhou, Ph.D.
> Xeotron Corporation
> E-mail xczhou@xeotron.com
>
>
>
>