This is a multi-part message in MIME format.
--------------699DF42EB4D24121B2344929
Content-Type: text/plain; charset=us-ascii
Content-Transfer-Encoding: 7bit

Our organization is working on creating large (10 mil) electrical
through vias in silicon wafers (525 um thick) and we're finding it a
little more difficult that originally anticipated.  The vias need to be
hermetic or nearly so.  They will form an RF ground path at GHz
frequencies and so need to have very low resistivity (Gold, Copper?)
sidewalls.  We are presently working on two approaches:

1.  Blind via.  A thick TiW pad is created on the top surface, then a
via is DRIE from the back surface and stops on the TiW.  Backside metal
(TiW/Au) finishes the job.

2.  Filled via.  Holes are etched thru the wafer (DRIE again), then
TiW/Au/TiW is deposited.  Glass frit is screened into the vias, then
fired.

I'm also looking for a replacement for DRIE.  Wet etch makes the vias
too large for our application, and excimer laser is even slower and more
expensive than DRIE (now that's a scary thought).

Does anyone know of any better approaches?

-John Ehmke

--------------699DF42EB4D24121B2344929
Content-Type: text/x-vcard; charset=us-ascii; name="vcard.vcf"
Content-Transfer-Encoding: 7bit
Content-Description: Card for Ehmke, John
Content-Disposition: attachment; filename="vcard.vcf"

begin:          vcard
fn:             John Ehmke
n:              Ehmke;John
org:            RF-MEMS
email;internet: j-ehmke@raytheon.com
title:          Product Engineer
tel;work:       972-344-3624
tel;fax:        972-344-3638
x-mozilla-cpt:  ;0
x-mozilla-html: TRUE
version:        2.1
end:            vcard


--------------699DF42EB4D24121B2344929--