durusmail: mems-talk: Anisotropic silicon etch question
Anisotropic silicon etch question
Ultrathin Chips: Call for paper and invitation
2001-08-22
Erik Jung (2 parts)
2001-08-20
2001-08-22
Anisotropic silicon etch question
Postlethwaite, Tim
2001-08-20
I am using EDP to anisotropically etch vias through a <100> silicon wafer.
My etch mask is a thermal oxide through which I've etched squares (ca. 650
microns on a side) using photoresist and a wet oxide etch.  After the EDP
etch has progressed through the wafer (about 390 microns thick), I hope to
have a 100 micron opening at the bottom (using the 54.7 degree sidewall
angle to calculate).  More frequently than not, I end up with rectangular,
not square vias.  The "rectangularness" of the holes can be seen both in the
top of the via and the opening at the bottom.  The long axis of the
rectangles are seen going in both possible directions on the same wafer.
The mask has been examined and the features are square.  The oxide mask on
the wafer has also been examined and the square openings in the oxide after
etching are also square.

Also, in most cases, the bottom and top opening are larger than expected and
the bottom opening size suggests a sidewall angle of greater than 54.7
degrees.

Does anyone have any ideas as to why I am not getting square vias?

Thanks!
Tim Postlethwaite
tpost@contech.com
Constellation Technology Corp.




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