Dear All,

I have fabricated through-wafer electroplated copper interconnects in 400 um
thick silicon wafer. The diameter of these copper filled vias is 50 um. Now
i am measuring the electrical properties of the electroplated interconnects.

I have used 4 point probe method to measure the electrical resistivity. A
pair of consective copper pillars interconencted at the bottom has been used
for measurement. After the measurement, the measured value of electrical
resistivity is about 10-12 times higher than the bulk electrical resistivity
(1.67 micro-ohm cm).Repeated measurement results shows the same higher value
of eletrical resistivity.

Literature shows that the sputtered copper films have lower electrical
resistivity that plated copper films so i believe this higher value of
resistivity should be related to grain size/orientation.

Can any one explain why the the electrical resistivity of electroplated
copper is so high compared to bulk copper?
What factors of electroplating specifically affect this value? how can this
resistivity can be reduced besides annealing?

I will be thankful to any one who can provide some useful details/journal
paper related to this problem.

Thanks,
Pradeep