Hello K.C.,

I routinely used thermally-grown (in wet O2) oxide as an etch mask against
25wt% TMAH while etching through hundreds of microns of (100) silicon.  I
experienced SiO2 etch rates on the order of 10nm/hr, with silicon etching at
approximately 30um/hr at 85C.  The quality of the oxide is a strong
indicator of the etch rate - dry thermal oxides etch slowest, followed by
wet oxides, then CVD oxides and I would assume that sputtered oxides etch
fastest.  SiO2 will generally etch faster in KOH than TMAH, but KOH offers
better anisotropy and slower etching in the Si (111) plane.

Au should be an effective etch mask in KOH and TMAH, if you can make it
stick.  Ni or 80/20 Ni/Cr should also work.  Pure Cr may also work, but I
haven't seen any literature on it.  If you're etching to create thin
structures, thermal oxide can be tricky because of the thermal stresses in
the oxide/silicon interface upon cooling from the growth temperature.  I've
experienced plastic deformation in the silicon near the SiO2/Si - the
silicon shrinks much more than the oxide during cooling, and the tensile
stresses in the silicon can exceed the plastic flow stress at, for example,
800C.

Feel free to contact me for more information.

Regards,

--
Brian C. Stahl
Graduate Student Researcher
UCSB Materials Research Laboratory
brian.stahl@gmail.com / bstahl@mrl.ucsb.edu
Cell: (805) 748-5839
Office: MRL 3117A


On Mon, Apr 20, 2009 at 6:49 PM, l j  wrote:

> Hello MEMS community,
>
> I am looking for input on problems with etch masking for long Si
> anisotropic etch.
> Recently I found myself needing to do anisotropic ~500 micron etch of Si
> (100) wafers, both sides polished. I do not have silicon nitride available
> as an option.
>
> I have studied recipes for etch and masks. Seems like the prescription for
> mask is CVD silicon nitride. For other mask options, recommendations seem to
> get less certain and more sketchy.
> Pulling together references I could find, I have tried KOH 50% 80C and TMAH
> 25% 80C. The etch itself works as expected on the Si (100).
>
> For masking I have tried Ti 500A / Au 2500A sputtered at 300C; Cr 500A / Au
> 2500A sputtered at 300C; SiO2 500A sputtered at 300C. Wafers were solvent
> cleaned and oxygen plasma cleaned prior to metal deposition.
>
> For the metal masks, after an hour or two in etch, it appears the adhesion
> layer Ti or Cr is being attacked, and with another hour or  two, the Au is
> almost floating off the Si, intact but without the Ti or Cr.
>
> For the SiO2 mask in the TMAH, it appears the TMAH got through the SiO2
> mask within an hour.
> So, are Ti or Cr and Au known to work, or not, as etch mask for long KOH or
> TMAH etch? Is there a solid reference in the literature? The behavior I saw
> reminds me of a description of anodic dissolution (M. Datta,
> “Anodic dissolution of metals at high rates,” IBM Journal of.. Research and
> Development, vol. 37, pp. 207–226, 1993.) I also found in memsnet a
> reference to the metal and Si combination resulting in a "primary cell"
> which removes the adhesion layer, but was a little sketch on details.
>
> Is sputtered SiO2 not dense enough to mask TMAH? Si/SiO2 selectivity of
> TMAH is supposed to be very high.
>
> Look forward to any insights.
> Thank you
> K.C.