To add what has been said already, many etchants are developed with
silicon in mind. Some may attack III-V semiconductors, or react to
produce undesirable byproducts on the surface (I've had the misfortune
of losing an InSb wafer due to a Cr etchant). If you can blanket coat
and then pattern down, adhesion, step coverage and substrate
cleanliness will be better. You can also heat the substrate, which you
can't if you have resist on it. If chemical selectivity does not allow
for an etch process, then lift-off is the only option. However,
lift-off is not all bad either. It can work very well, even with
sputter deposition, by using a bilayer resist process.




On Mon, Feb 28, 2011 at 1:37 PM, Luciani, Vincent
 wrote:
> Hello Andy,
>
> Large scale silicon chip processes use the etch process for a few reasons..
Primarily because the metal must be sputtered and sputtered metal is not
conducive to a good lift-off process.
>
> Contributing causes:
>
> Sputtered Al with 1% Si (and other alloys) is typical to avoid Al spiking and
compounds like that can't be evaporated.
>
> Sputtering gives good low stress step coverage. This same conformality which
is good for step coverage is bad for lift-off.
>
> Sputtering can fill without keyholes, large aspect ratio holes.
>
> Low stress step coverage is critical for reliability and is specified in all
Mil. and space specs.
>
> A robust deposition, lithography and RIE etch are easier in high volume (for
Si) than lift-off is (process control and logistics).
>
> The contact areas can be meticulously chemically cleaned, sputter cleaned and
covered with metal before any chance of contamination (low contact resistance).
>
> Good luck,
>
> Vince