durusmail: mems-talk: etch si condition
etch si condition
2013-03-21
2013-03-23
etch si condition
Michael Martin
2013-03-23
Charles,
   Assuming this is a capacitively coupled reactor, you might want to
increase your pressure so that you decrease sputtering of your mask, say
100-300mT. We typically use CF4 +20%O2 for silicon etching though SF6+O2
(10-20%) should work too.  O2 is added to scavenge either the carbon or
sulfur.  In any event, regular RIE is an isotropic etch, you will have a
horizontal etch equal to the depth.  If you need anisotropic you should
switch to DRIE.

Cheers,
   Michael


On Wed, Mar 20, 2013 at 11:15 PM, Charles Tang  wrote:

> Hi, guys,
>
> Where can I get a RIE dry etch condition for Si nano pattern etching?
> I used normal condition such as CHF3 or SF6, 80W RIE power and 20 mTorr
> for the etching,
> but my nano patterned Cr mask was totally destroyed.
>
> BTW, if I want to have a little bit vertical (not so vertical, I can
> accept some undercut) sidewall for 2 um Si trench ( 2um depth),
> can normal RIE (not ICP) been used for this etching?
>
> If you have some experience, please kindly share me some tricks.
>
> Thanks.
>
> Best regards.
>
> Charles
>
> Dept. of Electronic Engineering
> City University of Hong Kong
> 83 Tat Chee Avenue, Kowloon, Hong Kong
> tqyhappy@ymail.com
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