Hi Connie, If you switch to <100> Si Wafers Your problem will go away.

Ed Knighton, Process Engineer
Constellation Technology Corp.

> -----Original Message-----
> From: Connie Kathleen Smith [SMTP:cksmith@ruf.rice.edu]
> Sent: Friday, January 04, 2002 1:40 PM
> To:   mems-talk@memsnet.org
> Subject:      [mems-talk] 110 Si etching with 20%KOH
>
> I am trying to fabricate a flow channel with vertical side walls using a
> <110> Si wafer.  When I etch all the way through the wafer (which is
> desired) the side walls are slanted.  The wafers are coated with SiO2 and
> Si3N4 as protective barriers during etching.  I expected to lose several
> microns vertically during etching but the slanted walls were unexpected.
>
> Thank you,
> Connie Smith
> Rice University
> Department of Chemical Engineering
> 6100 Main MS 362
> Houston, TX  77005
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