durusmail: mems-talk: 110 Si etching with 20%KOH
110 Si etching with 20%KOH
110 Si etching with 20%KOH
Mighty Platypus
2002-01-14
Hi Connie,
One of the people in my group uses DRIE to etch all the way through a
<110> wafer, and then "polishes" the side walls using KOH. Depending on
what sort of difficulties you're having this may help.

Jesse Fowler
  UCLA/MAE Dept., 420 Westwood Plaza, Room 18-121, ENGR IV
  Los Angeles, CA 90095-1597 | (310)825-3977
"Rule #6: There is no rule #6" -- Monty Python
"ARTICLE SIX:  THIS ARTICLE IS ABOLISHED" -- Constitution of Afghanistan

On Mon, 7 Jan 2002, Connie Kathleen Smith wrote:

> >From literature and others' suggestions I was led to believe that to get
> vertical walls I would have to use 110 Si wafers.  The channel I am
> etching is only about 200um wide and 500um deep.
>
> Connie Smith
> Rice University
>
>
> On Mon, 7 Jan 2002, Knighton, Ed wrote:
>
> > Hi Connie, If you switch to <100> Si Wafers Your problem will go away.
> >
> > Ed Knighton, Process Engineer
> > Constellation Technology Corp.
> >
> > > -----Original Message-----
> > > From:     Connie Kathleen Smith [SMTP:cksmith@ruf.rice.edu]
> > > Sent:     Friday, January 04, 2002 1:40 PM
> > > To:       mems-talk@memsnet.org
> > > Subject:  [mems-talk] 110 Si etching with 20%KOH
> > >
> > > I am trying to fabricate a flow channel with vertical side walls using a
> > > <110> Si wafer.  When I etch all the way through the wafer (which is
> > > desired) the side walls are slanted.  The wafers are coated with SiO2 and
> > > Si3N4 as protective barriers during etching.  I expected to lose several
> > > microns vertically during etching but the slanted walls were unexpected.
> > >
> > > Thank you,
> > > Connie Smith
> > > Rice University
> > > Department of Chemical Engineering
> > > 6100 Main MS 362
> > > Houston, TX  77005
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