durusmail: mems-talk: Etching SOI wafer from back side
Etching SOI wafer from back side
2010-05-05
2010-05-05
2010-05-05
2010-05-06
2010-05-07
Etching SOI wafer from back side
weiquan yang
2010-05-06
Dear all,

Thank you for your reply. The top Si layer of SOI is only 300 nm and with
pattern, therefore I could not grow thermal SiO2 on top. For my purpose, one
way is to put a glass substrate on top side of SOI and seal the edge with
some polymer. I don't know wheather there is such kind of polymer which can
suvive in base (KOH or TMAH) and be easy to remove afterwards.

Regards

Weiquan Yang
EE department, University of Texas at Arlington

2010/5/6 Om Suwal 

> Dear Kagan,
>
> In my experience, the use of thermally grown oxide does stand well as etch
> mask for both TMAH . The oxide etch rate is ~2A/min for TMAH @80C.
> Thermally
> grown >3000 A oxide is sufficient as etch mask to etch for 500 um
> Si substrate of SOI.
>
> Regards
> Om
>
> On Thu, May 6, 2010 at 3:44 AM, Kagan Topalli <
> ktopalli@electroscience.osu.edu> wrote:
>
> > Hi,
> >
> > PECVD nitride and oxides cannot withstand several hours of KOH or TMAH
> > etching. LPCVD nitride or thermally grown oxide might be the choices for
> > masking KOH or TMAH etching.
> >
> > Regards.
> >
> > --
> > Kagan Topalli
>
> --
> Om Krishna Suwal
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