Hello people,

At the moment we are trying to build planar inductivities on an n-type
Si-wafer. Currently, there is an SiO2-insulator of about 50nm thickness
between substrate and the structured, sputtered Cu-Layer that forms the
inductivity.

Unfortunately, a parasitic capacitance of some dozen nF can be measured
while trying to measure the completed inductivities. Can anybody give me an
idea for being able to explain this problem?

Thanks in advance and best regards, Chris