Dear Abdullah,

I will send you the listing of available SOI wafers separately as
attachment.
On your etch problem, it is highly likely that you have a 'glass' layer
between the device and oxide that is preventing the etching. One
suggestion might be to use a dilute HF ( 5 to 1) slow etch to get
through this. As you know that HF can undercut and degrade the Si02 so
you need to be careful with this process. I am not sure who is
manufacturing this product so cant suggest whom to contact for more
info.
As far as you 650C 4 hour re-oxidation, I would not think that this
would create any problem in the interface layer. All BESOI wafers are
annealed after the wafer bonding at much higher temps without this kind
of etching problem.

You might find out the manufacturer of the product and then contact them
for a better understanding of the problem that you are seeing.

I will send you the updated listing shortly

Best Regards,

Ken Smith

Abdullah Tashtoush wrote:
>
> Dear Ken,
> I will be so grateful if you send these list.
> I think it is a glass layer, because the wafer was immersed for along time
> but no more etching was showing up, do you have any idea about how can we
> remove such glass because BOE it didn't remove this layer, either.  and one
> more thing just for curiosity, does re-oxidize SOI wafer affect the
> structure of the wafer, do you think re-oxidation ( thermal wet oxidation)
> might be reason to grow such layer, ( the temperature for oxidation that we
> use is around 650C for 4 hour), is there specific procedures  to oxidize SOI
> wafer.
>
> best regards
>
> BigBangwidth
> the exabit netOpticalTM company
>
> Abdullah Tashtoush
> MEMS Process Engineer
> Tel: (780) 490-4800 Ext. (227)
> Cell:(780) 953-0702
> Fax: (780) 430-8545
> atashtoush@BigBangwidth.com
> www.BigBangwidth.com
>
> -----Original Message-----
> From: Kenneth Smith [mailto:kasmith2@ix.netcom.com]
> Sent: Tuesday, July 31, 2001 6:16 PM
> To: Abdullah Tashtoush
> Subject: Re: [mems-talk] (no subject)
>
> Dear Abdullah,
>
> Should you have a need for Si Wafers or want to review my Excess SOI
> (BESOI) prime wafer listing, let me know.
>
> Regards,
>
> Ken Smith
>
> > Abdullah Tashtoush wrote:
> >
> > Dear MEMS research,
> > when TMAH or EDP used as an etchant, and  SOI 40 um wafer was used, I
> > figured out that the etch stop and it didn't hit the buried Silicon
> > dioxide and a layer with thickness  based up on SEM photo ~10-15um, do
> > you have any idea about this issue , if so would you please tell me
> > what this layer is, and how can we get rid of it, and  really I
> > appreciate  if you tell me about the reason that causes this layer.
> > thanks a lot.
> >
> > BigBangwidth
> > the exabit netOpticalTM company
> >
> > Abdullah Tashtoush
> > MEMS Process Engineer

Ken Smith

Kmbh Associates

4968 Charter Road
Rocklin, CA  95765  USA
510-714-5055 Efax- 510 217 4421 or 561 658 6136

High Purity Float Zone and Specialty CZ Silicon  for Power, IR and
Mirror Optics, Optoelectronics, MEMS, SOI, and other Semiconductor
applications. Service in SOI, Polishing SSP and DSP.