I'd disagree - lift-off is not in itself CMOS-incompatible - it's just
very impractical compared with etch-back.  In fact, off the top of my
head, I really can't think of any *process* which is genuinely not
CMOS-compatible (I haven't thought about it too long though!).  You said
yourself that lift-off is not 'usually' used for CMOS - correct - that
really rules it out as not CMOS-compatible, doesn't it?  Another process
in that kind of category is e-beam lithography.  Virtually unknown in
commercial CMOS because it's serial process rather than parallel and
therefore destroys your output volume and profit margin, but there's
nothing truly incompatible about it.

What makes a process CMOS-incompatible is mainly stuff like the
materials used and the thermal budget.  For example, CMOS fabrication
will invariably involve thermal processing well above 1000C, for field
oxide growth or activation of implanted dopants.  Anything you add to
your wafer will need to survive that kind of treatment and also not
cause contamination to the fab line.  A very crude example would be
working with a GaAs wafer, which will decompose at much lower
temperatures and destroy your fab line.  You could maybe also include
some of the worse contaminants, like sodium, which diffuses like crazy
and will again wreck your expensive equipment.  A subtler example of
'CMOS-incompatible' might be a badly-designed process flow, where you
put down a metal contact then have to grow a thick oxide at temperatures
which trash the contact.

One more thought before hitting 'send' - a CMOS engineer would curse (or
laugh) if you design a process which involves taking your wafer away
from the sealed fab line, doing something to it in your lab, and then
putting it back in.  So on that level, anything that can't be
incorporated into a fab line is not CMOS-compatible.

That's how I see it anyway!

Andy

Yu Chen wrote:
> for a standard CMOS cleanroom.
> that materials are allowed and not allowed?
>
> I know that CMOS cleanroom usually do not use liftoff process.
> Is there any other process are not prefered in CMOS cleanroom, but
> frequently used in other lower level lab?
>
> best
>
> Yu CHEN