Hi Nahid,
   You can reduce pinholes by increasing the temperature of the
deposition.  Of course this might cause problems with Au diffusion so you
may need to add a diffusion barrier.

-Michael


On Mon, Apr 29, 2013 at 6:49 PM, nahid vahabi wrote:

> Hello all,
> I deposit a 250 nm PECVD SiN layer as the dielectric between two gold
> layers and the metal layers seem to be short through the nitride each time.
> I increased the nitride thickness to 400 nm and still the same. I gathered
> that PECVD nitride is quite notorious for the pinholes so I multi-layered
> the nitride (6 times of 40 nm each) to get rid of pinholes. It worked only
> on 1 wafer and then the same problem again. So I appreciate any comments on
> this and whether you think changing the dielectric is a good option.
>
> Thank you,
> Nahid
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